DMA channels transfer data to and from main system memory with minimal burden on the system CPU. Each channel controls itself and any attached I/O devices by executing instructions called channel commands. Channel commands are organized into very simple programs called channel programs, also referred to as a “buffer descriptor list” in a descriptor based DMA system such as the DBDMA system created by Apple Computer, Inc., the assignee of the present application.
A DMA engine or controller may control operation of one or more channels. The DMA controller may contain one register file which stores the current channel program pointers for each channel, and another register file which contains the current context (address, count, and flags) for each of the channels. An example of such an implementation is the Apple Grand Central I/O Controller which services eleven DMA channels.
The function of the DMA controller is to arbitrate data transfer requests from various I/O devices in the system. These devices may operate only in slave mode DMA, that is, they may make requests which indicate that they have data in receive registers which is available to be received by the system, or that they have space available in transmission registers for data to be sent by the system. Also, the I/O device may indicate that either a transmit or receiver operation is complete by the generation of status information such as an interrupt which would normally require the attention of host processor.
It would be beneficial to have a DMA controller which could handle data and status information without calling on the host processor. In particular, it would be useful to have a DMA controller which is able to process multiple complete transmit or receive operations without calling on the host processor.